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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-11-10 12:12:33 -0800 |
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| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-11-10 13:07:29 -0800 |
| commit | 544ef42e40aa87d076595c275edabf13951aadf5 (patch) | |
| tree | 257959df71e5dfaf80a4527070f5213d2789f901 /llvm/lib/CodeGen | |
| parent | 438a27f2e56a9753d4cc8477a1f1c306edc4c885 (diff) | |
| download | llvm-544ef42e40aa87d076595c275edabf13951aadf5.zip llvm-544ef42e40aa87d076595c275edabf13951aadf5.tar.gz llvm-544ef42e40aa87d076595c275edabf13951aadf5.tar.bz2 | |
[AMDGPU] Set default op_sel_hi on accvgpr read/write
These are opsel opcodes with op_sel actually being ignored.
As a such op_sel_hi needs to be set to default 1 even though
these bits are ignored. This is compatibility change.
Differential Revision: https://reviews.llvm.org/D91202
Diffstat (limited to 'llvm/lib/CodeGen')
0 files changed, 0 insertions, 0 deletions