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| author | Albion Fung <albionapc@gmail.com> | 2020-08-12 18:26:43 -0500 |
|---|---|---|
| committer | Albion Fung <albionapc@gmail.com> | 2020-08-12 18:26:58 -0500 |
| commit | 3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8 (patch) | |
| tree | 9e7e4e5c9288c3254f3e189fed8e50c08227e0df /llvm/lib/CodeGen | |
| parent | a31c89c1b7a0a2fd3e2c0b8a587a60921abf4abd (diff) | |
| download | llvm-3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8.zip llvm-3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8.tar.gz llvm-3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8.tar.bz2 | |
[PowerPC] Implement Vector Shift Builtins
This patch implements the builtins for the vector shifts (shl, srl, sra), and
adds the appropriate test cases for these builtins. The builtins utilize the
vector shift instructions introduced within ISA 3.1.
Differential Revision: https://reviews.llvm.org/D83338
Diffstat (limited to 'llvm/lib/CodeGen')
0 files changed, 0 insertions, 0 deletions