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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-09-21 10:42:03 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-09-22 09:51:15 -0400 |
| commit | 94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72 (patch) | |
| tree | 8ec4d1605b39e27926c3b7b15bedf148dc63b343 /llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | |
| parent | c2e76f914c9ac0dd15e4a8040a5e277333f91f97 (diff) | |
| download | llvm-94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72.zip llvm-94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72.tar.gz llvm-94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72.tar.bz2 | |
MachineVerifier: Verify REG_SEQUENCE
Somehow there was no verification of this, other than an ad-hoc
assertion in TwoAddressInstructions.
Diffstat (limited to 'llvm/lib/CodeGen/TwoAddressInstructionPass.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 3805221..a487ec3 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1887,11 +1887,6 @@ void TwoAddressInstructionPass:: eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { MachineInstr &MI = *MBBI; Register DstReg = MI.getOperand(0).getReg(); - if (MI.getOperand(0).getSubReg() || DstReg.isPhysical() || - !(MI.getNumOperands() & 1)) { - LLVM_DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI); - llvm_unreachable(nullptr); - } SmallVector<Register, 4> OrigRegs; if (LIS) { |