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| author | Mehdi Amini <joker.eph@gmail.com> | 2020-12-30 00:19:31 +0000 |
|---|---|---|
| committer | Mehdi Amini <joker.eph@gmail.com> | 2020-12-30 00:19:38 +0000 |
| commit | 58ce477676c7bd9c6cee0c6d05f2708b4e178ff3 (patch) | |
| tree | add29cf2fbb7e2346a911777c06f63d1822953f9 /llvm/lib/CodeGen/TargetPassConfig.cpp | |
| parent | 2c8f5bd53945a209cd3cd851c63df3713fa0f9bd (diff) | |
| download | llvm-58ce477676c7bd9c6cee0c6d05f2708b4e178ff3.zip llvm-58ce477676c7bd9c6cee0c6d05f2708b4e178ff3.tar.gz llvm-58ce477676c7bd9c6cee0c6d05f2708b4e178ff3.tar.bz2 | |
Fix DRR pattern when attributes and operands are interleaved and a dag subtree appears in the rewrite
This fixes an incorrect fatal error in TableGen. This code probably comes
from before attributes were allowed to interleave with operands in ODS.
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D93915
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
0 files changed, 0 insertions, 0 deletions