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authorSimon Moll <simon.moll@emea.nec.com>2021-04-30 13:43:48 +0200
committerSimon Moll <simon.moll@emea.nec.com>2021-04-30 15:47:28 +0200
commit43bc584dc05e24c6d44ece8e07d4bff585adaf6d (patch)
tree7fa48799edf45ea95d755f39a8bbd8cf6ba88f52 /llvm/lib/CodeGen/TargetPassConfig.cpp
parent181c492ee72c2234e50a60dda467a587f1e8dc08 (diff)
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[VP,Integer,#2] ExpandVectorPredication pass
This patch implements expansion of llvm.vp.* intrinsics (https://llvm.org/docs/LangRef.html#vector-predication-intrinsics). VP expansion is required for targets that do not implement VP code generation. Since expansion is controllable with TTI, targets can switch on the VP intrinsics they do support in their backend offering a smooth transition strategy for VP code generation (VE, RISC-V V, ARM SVE, AVX512, ..). Reviewed By: rogfer01 Differential Revision: https://reviews.llvm.org/D78203
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetPassConfig.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 6e80235..b5e8f9e 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -864,6 +864,11 @@ void TargetPassConfig::addIRPasses() {
if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
addPass(createPartiallyInlineLibCallsPass());
+ // Expand vector predication intrinsics into standard IR instructions.
+ // This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
+ // passes since it emits those kinds of intrinsics.
+ addPass(createExpandVectorPredicationPass());
+
// Add scalarization of target's unsupported masked memory intrinsics pass.
// the unsupported intrinsic will be replaced with a chain of basic blocks,
// that stores/loads element one-by-one if the appropriate mask bit is set.