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| author | quic_hchandel <165007698+hchandel@users.noreply.github.com> | 2025-01-23 10:14:25 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-23 10:14:25 +0530 |
| commit | 163935a48df69bde944fae2b4581541dab30c730 (patch) | |
| tree | 245858613552f5c5c31219ce7fcd5b3a96f5b7af /llvm/lib/CodeGen/TargetPassConfig.cpp | |
| parent | aa273fd83eccb55215f4cb18285f8462a1013f5c (diff) | |
| download | llvm-163935a48df69bde944fae2b4581541dab30c730.zip llvm-163935a48df69bde944fae2b4581541dab30c730.tar.gz llvm-163935a48df69bde944fae2b4581541dab30c730.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)
This extension adds eight 48 bit load store instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
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Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
0 files changed, 0 insertions, 0 deletions