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author | Jay Foad <jay.foad@amd.com> | 2020-01-06 11:22:51 +0000 |
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committer | Jay Foad <jay.foad@amd.com> | 2020-01-22 14:28:24 +0000 |
commit | e0f0d0e55cc7d389ad0692fbc9678e7895978355 (patch) | |
tree | dbf214c788e8e0a01cc3dbca418d8336fee60eff /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
parent | 70096ca111ee2848fb2e29a7cb3e4fb7e3ba9ef9 (diff) | |
download | llvm-e0f0d0e55cc7d389ad0692fbc9678e7895978355.zip llvm-e0f0d0e55cc7d389ad0692fbc9678e7895978355.tar.gz llvm-e0f0d0e55cc7d389ad0692fbc9678e7895978355.tar.bz2 |
[MachineScheduler] Allow clustering mem ops with complex addresses
The generic BaseMemOpClusterMutation calls into TargetInstrInfo to
analyze the address of each load/store instruction, and again to decide
whether two instructions should be clustered. Previously this had to
represent each address as a single base operand plus a constant byte
offset. This patch extends it to support any number of base operands.
The old target hook getMemOperandWithOffset is now a convenience
function for callers that are only prepared to handle a single base
operand. It calls the new more general target hook
getMemOperandsWithOffset.
The only requirements for the base operands returned by
getMemOperandsWithOffset are:
- they can be sorted by MemOpInfo::Compare, such that clusterable ops
get sorted next to each other, and
- shouldClusterMemOps knows what they mean.
One simple follow-on is to enable clustering of AMDGPU FLAT instructions
with both vaddr and saddr (base register + offset register). I've left
a FIXME in the code for this case.
Differential Revision: https://reviews.llvm.org/D71655
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
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