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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-02-19 16:13:26 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-02-19 16:13:26 +0000 |
| commit | acb20adbe4a155072074c3425b7d37caf6167872 (patch) | |
| tree | 01ef9b493b41f31e5299ceba7f4df63f9a2f350a /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
| parent | aa7bca15f04b01bf0114b8bcb3ed8683115a460b (diff) | |
| download | llvm-acb20adbe4a155072074c3425b7d37caf6167872.zip llvm-acb20adbe4a155072074c3425b7d37caf6167872.tar.gz llvm-acb20adbe4a155072074c3425b7d37caf6167872.tar.bz2 | |
[mips] In the integrated assembler, select the default feature bits by changing the CPU value.
This is consistent with the way CodeGen acheives this. However, CodeGen
always selects mips32 (even when the architecture is mips64).
llvm-svn: 201694
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
0 files changed, 0 insertions, 0 deletions