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| author | Jay Foad <jay.foad@amd.com> | 2020-04-17 10:28:47 +0100 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2020-04-17 14:37:11 +0100 |
| commit | 96712d6ef2c970ca3f5562be23d78d7df6360b4d (patch) | |
| tree | 6cf24c9d54cec0ceab36da2407e0c86029762825 /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
| parent | 166467e8221d202ad3e7b8c156e99f7a6def35e0 (diff) | |
| download | llvm-96712d6ef2c970ca3f5562be23d78d7df6360b4d.zip llvm-96712d6ef2c970ca3f5562be23d78d7df6360b4d.tar.gz llvm-96712d6ef2c970ca3f5562be23d78d7df6360b4d.tar.bz2 | |
[AMDGPU] Simplify SIRegisterInfo::getRegSplitParts
Summary:
Use more logic and fewer tables. This reduces the line count and
reduces the effort required to introduce more register classes of
different sizes in future.
Reviewers: arsenm, rampitec, nhaehnle
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78351
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
0 files changed, 0 insertions, 0 deletions