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| author | Pengxuan Zheng <pzheng@quicinc.com> | 2020-04-24 13:15:51 -0700 |
|---|---|---|
| committer | Pengxuan Zheng <pzheng@quicinc.com> | 2020-04-24 13:27:43 -0700 |
| commit | 79702dd349f31c0c67bf35f36435fdc843fcd052 (patch) | |
| tree | f1b3de2fc7a4ba234003c5fafc00471fa9afbc7f /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
| parent | 97ecd91e2025f23c3ed38594454aeb7027ad82b7 (diff) | |
| download | llvm-79702dd349f31c0c67bf35f36435fdc843fcd052.zip llvm-79702dd349f31c0c67bf35f36435fdc843fcd052.tar.gz llvm-79702dd349f31c0c67bf35f36435fdc843fcd052.tar.bz2 | |
[RISCV] Add instruction definition for dret
Summary:
The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.
https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: apazos
Subscribers: jfb, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78583
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
0 files changed, 0 insertions, 0 deletions