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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-07-21 23:24:02 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-08-06 09:41:14 -0400 |
| commit | 53162567090251e98b14f979ee2f69669cec3ddd (patch) | |
| tree | c01c8a22a6802ff368b64fb19d5734fee6e931bf /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
| parent | 1de43bd6df74fb4cd8c25020afa1dd14ecf08527 (diff) | |
| download | llvm-53162567090251e98b14f979ee2f69669cec3ddd.zip llvm-53162567090251e98b14f979ee2f69669cec3ddd.tar.gz llvm-53162567090251e98b14f979ee2f69669cec3ddd.tar.bz2 | |
AMDGPU/GlobalISel: Fix assert on copy to vcc
This was trying to constrain a physical register. By the verifier's
understanding, it's impossible to have a 1-bit copy to vcc/vcc_lo so
don't try to handle physregs.
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
0 files changed, 0 insertions, 0 deletions