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| author | Craig Topper <craig.topper@intel.com> | 2020-07-09 10:28:42 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-07-09 10:40:09 -0700 |
| commit | 3e75912005cbbdc7c7244b73319cb7441e64682f (patch) | |
| tree | 626c55a9afe9ebf677ec315487cfb382322ad222 /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
| parent | 6f7727db478b452a262b2beea2beceef096eb68c (diff) | |
| download | llvm-3e75912005cbbdc7c7244b73319cb7441e64682f.zip llvm-3e75912005cbbdc7c7244b73319cb7441e64682f.tar.gz llvm-3e75912005cbbdc7c7244b73319cb7441e64682f.tar.bz2 | |
[X86] Directly emit X86ISD::BLENDV instead of VSELECT in a few places that were emitting sign bit tests.
Technically a VSELECT expects a vector of all 1s or 0s elements
for its condition. But we aren't guaranteeing that the sign bit
and the non sign bits match in these locations. So we should use
BLENDV which is more relaxed.
Differential Revision: https://reviews.llvm.org/D83447
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
0 files changed, 0 insertions, 0 deletions