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| author | quic_hchandel <quic_hchandel@quicinc.com> | 2025-07-15 12:13:57 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-15 12:13:57 +0530 |
| commit | 0be51cff91293eb0f4ee11088d4d9edade590b48 (patch) | |
| tree | 67809519e2ba1a072cce385c6ed99adb0bc99ea5 /llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | |
| parent | 977cfea786401eab2b167307221a15fa6747e28e (diff) | |
| download | llvm-0be51cff91293eb0f4ee11088d4d9edade590b48.zip llvm-0be51cff91293eb0f4ee11088d4d9edade590b48.tar.gz llvm-0be51cff91293eb0f4ee11088d4d9edade590b48.tar.bz2 | |
[RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (#148121)
Add CodeGen patterns for conditional load immediate instructions
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp')
0 files changed, 0 insertions, 0 deletions