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| author | Craig Topper <craig.topper@sifive.com> | 2023-04-05 18:52:28 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-04-05 18:52:28 -0700 |
| commit | f1924d965abb043075fe000ebb7d8ca428fda137 (patch) | |
| tree | 1133bfc2c0e67bc12650208bf8f333f0427def4e /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 6510fa90a0c12c18f39601c6f4f70bc7e916fe29 (diff) | |
| download | llvm-f1924d965abb043075fe000ebb7d8ca428fda137.zip llvm-f1924d965abb043075fe000ebb7d8ca428fda137.tar.gz llvm-f1924d965abb043075fe000ebb7d8ca428fda137.tar.bz2 | |
[SelectionDAG] Expand VP SDNodes by default.
Differential Revision: https://reviews.llvm.org/D147643
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index ac27168..6d006ff 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -875,10 +875,10 @@ void TargetLoweringBase::initActions() { // Named vector shuffles default to expand. setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); - // VP_SREM/UREM default to expand. - // TODO: Expand all VP intrinsics. - setOperationAction(ISD::VP_SREM, VT, Expand); - setOperationAction(ISD::VP_UREM, VT, Expand); + // VP operations default to expand. +#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \ + setOperationAction(ISD::SDOPC, VT, Expand); +#include "llvm/IR/VPIntrinsics.def" } // Most targets ignore the @llvm.prefetch intrinsic. |