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| author | Craig Topper <craig.topper@sifive.com> | 2025-08-22 16:36:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-22 16:36:11 -0700 |
| commit | c9e5b6a03b23af963d2a0ebb82a9061372c47ff5 (patch) | |
| tree | d22e2a69f16f3a4587f2d4506ad1b2029d7758d7 /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 43f05fb57f7cca984892a9f131851352b3f182b6 (diff) | |
| download | llvm-c9e5b6a03b23af963d2a0ebb82a9061372c47ff5.zip llvm-c9e5b6a03b23af963d2a0ebb82a9061372c47ff5.tar.gz llvm-c9e5b6a03b23af963d2a0ebb82a9061372c47ff5.tar.bz2 | |
[RISCV] Rename VALUrVV/VALUrVX/VALUrVF tablegen clases. NFC (#154989)
Rename them to VMACVV/VX/VF. The 'r' previously meant "reversed" since
their operand order is vs1, vs2 where other vector instructions are vs2,
vs1.
These instructions are also ternary and have a tied register. "MAC"
better reflects this property.
While doing this I also found a missing earlyclobber in VWMAC_MV_X, but
I don't think this has any effect since we use pseudos for regalloc.
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
0 files changed, 0 insertions, 0 deletions