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| author | David Sherwood <david.sherwood@arm.com> | 2020-06-11 07:47:23 +0100 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2020-06-18 09:54:16 +0100 |
| commit | 7e30ef77f6749695e79a8e43a1d1780ef57a52d2 (patch) | |
| tree | e69f3b3fe4748df4730da3961b16eb380a2213fb /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 6d18c2067ef1f2450078c115966ebb2699b0558c (diff) | |
| download | llvm-7e30ef77f6749695e79a8e43a1d1780ef57a52d2.zip llvm-7e30ef77f6749695e79a8e43a1d1780ef57a52d2.tar.gz llvm-7e30ef77f6749695e79a8e43a1d1780ef57a52d2.tar.bz2 | |
[CodeGen] Fix warnings in getVectorTypeBreakdown
Added NextPowerOf2() routine to TypeSize and rewritten the code
in getVectorTypeBreakdown to avoid warnings being generated.
Differential Revision: https://reviews.llvm.org/D81578
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 6ec6498..c822092 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1474,14 +1474,14 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT MVT DestVT = getRegisterType(Context, NewVT); RegisterVT = DestVT; - unsigned NewVTSize = NewVT.getSizeInBits(); - // Convert sizes such as i33 to i64. - if (!isPowerOf2_32(NewVTSize)) - NewVTSize = NextPowerOf2(NewVTSize); - - if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. + if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. + TypeSize NewVTSize = NewVT.getSizeInBits(); + // Convert sizes such as i33 to i64. + if (!isPowerOf2_32(NewVTSize.getKnownMinSize())) + NewVTSize = NewVTSize.NextPowerOf2(); return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); + } // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. |