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| author | Abhilash Majumder <30946547+abhilash1910@users.noreply.github.com> | 2025-02-11 14:24:46 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-11 14:24:46 +0530 |
| commit | 6a961dc03d802fb1f34b2b0cd8d09f427382dbdb (patch) | |
| tree | 9563651fbe882d204da50701d056e07098ee0263 /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 99e1308c41b24e2422324d68be28e5370196e5d6 (diff) | |
| download | llvm-6a961dc03d802fb1f34b2b0cd8d09f427382dbdb.zip llvm-6a961dc03d802fb1f34b2b0cd8d09f427382dbdb.tar.gz llvm-6a961dc03d802fb1f34b2b0cd8d09f427382dbdb.tar.bz2 | |
[NVPTX] Add intrinsics for prefetch.* (#125887)
\[NVPTX\] Add Prefetch intrinsics
This PR adds prefetch intrinsics with the relevant eviction priorities.
* Lit tests are added as part of prefetch.ll
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst.
For more information, refer PTX ISA
`<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prefetch-prefetchu>`_.
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Co-authored-by: abmajumder <abmajumder@nvidia.com>
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
0 files changed, 0 insertions, 0 deletions