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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-11-17 12:12:54 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-11-17 12:41:48 +0000 |
| commit | 5fedbd5b181523541331eee3008467a39f0334cb (patch) | |
| tree | f22878556fc56f692cb6277a290d614648217faf /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 964536cf04e29ebc125cdb44484e2c2cd8e0bd9b (diff) | |
| download | llvm-5fedbd5b181523541331eee3008467a39f0334cb.zip llvm-5fedbd5b181523541331eee3008467a39f0334cb.tar.gz llvm-5fedbd5b181523541331eee3008467a39f0334cb.tar.bz2 | |
[DAG] SimplifyDemandedVectorElts - zero_extend_vector_inreg(and(x,c)) -> and(x,c')
If we've only demanded the 0'th element, and it comes from a (one-use) AND, try to convert the zero_extend_vector_inreg into a mask and constant fold it with the AND.
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
0 files changed, 0 insertions, 0 deletions