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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-03-05 19:37:53 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-03-05 19:37:53 +0000 |
| commit | 4200cc95b4a12ba275ce60d52056e283729a551e (patch) | |
| tree | 165630f13a9ceb6adb996b8f6cdf6e9425502462 /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | e5bf7694432e3253b6d46bbc5d65318373beb5ff (diff) | |
| download | llvm-4200cc95b4a12ba275ce60d52056e283729a551e.zip llvm-4200cc95b4a12ba275ce60d52056e283729a551e.tar.gz llvm-4200cc95b4a12ba275ce60d52056e283729a551e.tar.bz2 | |
[ARM] Enable vector extload combine for legal types.
This commit enables forming vector extloads for ARM.
It only does so for legal types, and when we can't fold the extension
in a wide/long form of the user instruction.
Enabling it for larger types isn't as good an idea on ARM as it is on
X86, because:
- we pretend that extloads are legal, but end up generating vld+vmov
- we have instructions like vld {dN, dM}, which can't be generated
when we "manually expand" extloads to vld+vmov.
For legal types, the combine doesn't fire that often: in the
integration tests only in a big endian testcase, where it removes a
pointless AND.
Related to rdar://19723053
Differential Revision: http://reviews.llvm.org/D7423
llvm-svn: 231396
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
0 files changed, 0 insertions, 0 deletions