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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-15 18:58:25 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-15 18:58:25 +0000 |
| commit | 1f2b727298de19a4e6de3fe28886628cec996b9b (patch) | |
| tree | 06f2d75fdc635560d5feb45cf73f65343585cbe5 /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | d202899431e49484d907608dbe74fa6d708bb07b (diff) | |
| download | llvm-1f2b727298de19a4e6de3fe28886628cec996b9b.zip llvm-1f2b727298de19a4e6de3fe28886628cec996b9b.tar.gz llvm-1f2b727298de19a4e6de3fe28886628cec996b9b.tar.bz2 | |
MVT: Add v3i16/v3f16 vectors
AMDGPU has some buffer intrinsics which theoretically could use
this. Some of the generated tables include the 3 and 4 element vector
versions of these rounded to 64-bits, which is ambiguous. Add these to
help the table disambiguate these.
Assertion change is for the path odd sized vectors now take for R600.
v3i16 is widened to v4i16, which then needs to be promoted to v4i32.
llvm-svn: 369038
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 9b28c1a..982e3185 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -824,7 +824,8 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); assert((LA == TypeLegal || LA == TypeSoftenFloat || - ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && + (NVT.isVector() || + ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) && "Promote may not follow Expand or Promote"); if (LA == TypeSplitVector) |