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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 16:16:12 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 16:16:12 +0000 |
commit | faeaedf8e938696497021adcd5925e5741c72f62 (patch) | |
tree | 66d3c65d42cfac2b080183c6c79562d0c205b23f /llvm/lib/CodeGen/SwiftErrorValueTracking.cpp | |
parent | 906d494b6e7eb0d8bde19bec2de7d93a9516ebe3 (diff) | |
download | llvm-faeaedf8e938696497021adcd5925e5741c72f62.zip llvm-faeaedf8e938696497021adcd5925e5741c72f62.tar.gz llvm-faeaedf8e938696497021adcd5925e5741c72f62.tar.bz2 |
GlobalISel: Remove unsigned variant of SrcOp
Force using Register.
One downside is the generated register enums require explicit
conversion.
llvm-svn: 364194
Diffstat (limited to 'llvm/lib/CodeGen/SwiftErrorValueTracking.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SwiftErrorValueTracking.cpp | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp b/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp index e59cd8e..96821ca 100644 --- a/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp +++ b/llvm/lib/CodeGen/SwiftErrorValueTracking.cpp @@ -22,7 +22,7 @@ using namespace llvm; -unsigned SwiftErrorValueTracking::getOrCreateVReg(const MachineBasicBlock *MBB, +Register SwiftErrorValueTracking::getOrCreateVReg(const MachineBasicBlock *MBB, const Value *Val) { auto Key = std::make_pair(MBB, Val); auto It = VRegDefMap.find(Key); @@ -46,7 +46,7 @@ void SwiftErrorValueTracking::setCurrentVReg(const MachineBasicBlock *MBB, VRegDefMap[std::make_pair(MBB, Val)] = VReg; } -unsigned SwiftErrorValueTracking::getOrCreateVRegDefAt( +Register SwiftErrorValueTracking::getOrCreateVRegDefAt( const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) { auto Key = PointerIntPair<const Instruction *, 1, bool>(I, true); auto It = VRegDefUses.find(Key); @@ -55,20 +55,20 @@ unsigned SwiftErrorValueTracking::getOrCreateVRegDefAt( auto &DL = MF->getDataLayout(); const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); - unsigned VReg = MF->getRegInfo().createVirtualRegister(RC); + Register VReg = MF->getRegInfo().createVirtualRegister(RC); VRegDefUses[Key] = VReg; setCurrentVReg(MBB, Val, VReg); return VReg; } -unsigned SwiftErrorValueTracking::getOrCreateVRegUseAt( +Register SwiftErrorValueTracking::getOrCreateVRegUseAt( const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) { auto Key = PointerIntPair<const Instruction *, 1, bool>(I, false); auto It = VRegDefUses.find(Key); if (It != VRegDefUses.end()) return It->second; - unsigned VReg = getOrCreateVReg(MBB, Val); + Register VReg = getOrCreateVReg(MBB, Val); VRegDefUses[Key] = VReg; return VReg; } @@ -129,7 +129,7 @@ bool SwiftErrorValueTracking::createEntriesInEntryBlock(DebugLoc DbgLoc) { // least by the 'return' of the swifterror. if (SwiftErrorArg && SwiftErrorArg == SwiftErrorVal) continue; - unsigned VReg = MF->getRegInfo().createVirtualRegister(RC); + Register VReg = MF->getRegInfo().createVirtualRegister(RC); // Assign Undef to Vreg. We construct MI directly to make sure it works // with FastISel. BuildMI(*MBB, MBB->getFirstNonPHI(), DbgLoc, @@ -177,7 +177,7 @@ void SwiftErrorValueTracking::propagateVRegs() { // Check whether we have a single vreg def from all predecessors. // Otherwise we need a phi. - SmallVector<std::pair<MachineBasicBlock *, unsigned>, 4> VRegs; + SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; SmallSet<const MachineBasicBlock *, 8> Visited; for (auto *Pred : MBB->predecessors()) { if (!Visited.insert(Pred).second) @@ -203,7 +203,7 @@ void SwiftErrorValueTracking::propagateVRegs() { VRegs.size() >= 1 && std::find_if( VRegs.begin(), VRegs.end(), - [&](const std::pair<const MachineBasicBlock *, unsigned> &V) + [&](const std::pair<const MachineBasicBlock *, Register> &V) -> bool { return V.second != VRegs[0].second; }) != VRegs.end(); @@ -227,7 +227,7 @@ void SwiftErrorValueTracking::propagateVRegs() { assert(UpwardsUse); assert(!VRegs.empty() && "No predecessors? Is the Calling Convention correct?"); - unsigned DestReg = UUseVReg; + Register DestReg = UUseVReg; BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY), DestReg) .addReg(VRegs[0].second); |