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| author | Vitaly Buka <vitalybuka@google.com> | 2023-07-26 15:41:17 -0700 |
|---|---|---|
| committer | Vitaly Buka <vitalybuka@google.com> | 2023-07-26 22:13:32 -0700 |
| commit | a496c8be6e638ae58bb45f13113dbe3a4b7b23fd (patch) | |
| tree | 4c1f5e42c8ce8af5fd33d022e653e874f80742c9 /llvm/lib/CodeGen/SplitKit.cpp | |
| parent | fa140fe211836653269ba279381a55c171b52584 (diff) | |
| download | llvm-a496c8be6e638ae58bb45f13113dbe3a4b7b23fd.zip llvm-a496c8be6e638ae58bb45f13113dbe3a4b7b23fd.tar.gz llvm-a496c8be6e638ae58bb45f13113dbe3a4b7b23fd.tar.bz2 | |
Revert "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
And dependent commits.
Details in D150388.
This reverts commit 825b7f0ca5f2211ec3c93139f98d1e24048c225c.
This reverts commit 7a98f084c4d121244ef7286bc6503b6a181d446e.
This reverts commit b4a62b1fa546312d882fa12dfdcd015177d66826.
This reverts commit b7836d856206ec39509d42529f958c920368166b.
No conflicts in the code, few tests had conflicts in autogenerated CHECKs:
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
Reviewed By: alexfh
Differential Revision: https://reviews.llvm.org/D156381
Diffstat (limited to 'llvm/lib/CodeGen/SplitKit.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SplitKit.cpp | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 83964ec..eee54f0 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -514,10 +514,10 @@ void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { VFP = ValueForcePair(nullptr, true); } -SlotIndex SplitEditor::buildSingleSubRegCopy( - Register FromReg, Register ToReg, MachineBasicBlock &MBB, - MachineBasicBlock::iterator InsertBefore, unsigned SubIdx, - LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) { +SlotIndex SplitEditor::buildSingleSubRegCopy(Register FromReg, Register ToReg, + MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, + unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) { + const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); bool FirstCopy = !Def.isValid(); MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc) .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy) @@ -536,8 +536,7 @@ SlotIndex SplitEditor::buildSingleSubRegCopy( SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { - const MCInstrDesc &Desc = - TII.get(TII.getLiveRangeSplitOpcode(FromReg, *MBB.getParent())); + const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); SlotIndexes &Indexes = *LIS.getSlotIndexes(); if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) { // The full vreg is copied. @@ -565,7 +564,7 @@ SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, SlotIndex Def; for (unsigned BestIdx : SubIndexes) { Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, BestIdx, - DestLI, Late, Def, Desc); + DestLI, Late, Def); } BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator(); @@ -1585,9 +1584,7 @@ bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI, if (BI.LiveIn && BI.LiveOut) return true; // No point in isolating a copy. It has no register class constraints. - MachineInstr *MI = LIS.getInstructionFromIndex(BI.FirstInstr); - bool copyLike = TII.isCopyInstr(*MI) || MI->isSubregToReg(); - if (copyLike) + if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike()) return false; // Finally, don't isolate an end point that was created by earlier splits. return isOriginalEndpoint(BI.FirstInstr); |