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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-03-04 10:04:14 +0700 |
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committer | GitHub <noreply@github.com> | 2025-03-04 10:04:14 +0700 |
commit | 8476a5d480304bf7bd934c660a159e1c6906a69d (patch) | |
tree | d59402054273ba2599da91acb0ec637a982dc6de /llvm/lib/CodeGen/SplitKit.cpp | |
parent | ce1a18e2c714f39fe72cd46aa04faed29ad23cb6 (diff) | |
download | llvm-8476a5d480304bf7bd934c660a159e1c6906a69d.zip llvm-8476a5d480304bf7bd934c660a159e1c6906a69d.tar.gz llvm-8476a5d480304bf7bd934c660a159e1c6906a69d.tar.bz2 |
SplitKit: Fix rematerialization undoing subclass based split (#122110)
This fixes an allocation failure in the new test.
In cases where getLargestLegalSuperClass can inflate the register class,
rematerialization could effectively undo a split which was done to
inflate
the register class, if the defining instruction can only write a
subclass
and the use can read the superclass.
Some of the x86 tests changes look like improvements, but some are
likely regressions.
I'm not entirely sure this is the correct place to fix this. It also
seems more complicated than necessary, but the decision to change
the register class is far removed from the point where the decision
to split the virtual register is made. I'm also also not sure if this
should be considering the register classes of all the use indexes
in getUseSlots, rather than just checking if this use index instruction
reads the register.
Diffstat (limited to 'llvm/lib/CodeGen/SplitKit.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SplitKit.cpp | 45 |
1 files changed, 42 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index f6e73e2..63ca45b 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -588,6 +588,38 @@ SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, return Def; } +bool SplitEditor::rematWillIncreaseRestriction(const MachineInstr *DefMI, + MachineBasicBlock &MBB, + SlotIndex UseIdx) const { + if (!DefMI) + return false; + + const MachineInstr *UseMI = LIS.getInstructionFromIndex(UseIdx); + if (!UseMI) + return false; + + Register Reg = Edit->getReg(); + const TargetRegisterClass *RC = MRI.getRegClass(Reg); + + // We want to find the register class that can be inflated to after the split + // occurs in recomputeRegClass + const TargetRegisterClass *SuperRC = + TRI.getLargestLegalSuperClass(RC, *MBB.getParent()); + + // We want to compute the static register class constraint for the instruction + // def. If it is a smaller subclass than getLargestLegalSuperClass at the use + // site, then rematerializing it will increase the constraints. + const TargetRegisterClass *DefConstrainRC = + DefMI->getRegClassConstraintEffectForVReg(Reg, SuperRC, &TII, &TRI, + /*ExploreBundle=*/true); + + const TargetRegisterClass *UseConstrainRC = + UseMI->getRegClassConstraintEffectForVReg(Reg, SuperRC, &TII, &TRI, + /*ExploreBundle=*/true); + + return UseConstrainRC->hasSubClass(DefConstrainRC); +} + VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex UseIdx, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) { @@ -609,9 +641,16 @@ VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI, LiveRangeEdit::Remat RM(ParentVNI); RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); if (Edit->canRematerializeAt(RM, OrigVNI, UseIdx, true)) { - Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late); - ++NumRemats; - DidRemat = true; + if (!rematWillIncreaseRestriction(RM.OrigMI, MBB, UseIdx)) { + Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late); + ++NumRemats; + DidRemat = true; + } else { + LLVM_DEBUG( + dbgs() << "skipping rematerialize of " << printReg(Reg) << " at " + << UseIdx + << " since it will increase register class restrictions\n"); + } } } if (!DidRemat) { |