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author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-05-16 13:15:27 +0000 |
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committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-05-16 13:15:27 +0000 |
commit | 73643b5041bbd90bc622b44fb50f0f9c15b6c8ce (patch) | |
tree | 198c3c17b093710d3009e1ed1d4f71dc25221494 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | |
parent | 2120748f770d9cd6c5ea8fd6f051c5c1ad425756 (diff) | |
download | llvm-73643b5041bbd90bc622b44fb50f0f9c15b6c8ce.zip llvm-73643b5041bbd90bc622b44fb50f0f9c15b6c8ce.tar.gz llvm-73643b5041bbd90bc622b44fb50f0f9c15b6c8ce.tar.bz2 |
[CodeGen] Add lround/llround builtins
This patch add the ISD::LROUND and ISD::LLROUND along with new
intrinsics. The changes are straightforward as for other
floating-point rounding functions, with just some adjustments
required to handle the return value being an interger.
The idea is to optimize lround/llround generation for AArch64
in a subsequent patch. Current semantic is just route it to libm
symbol.
llvm-svn: 360889
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 45a9a25..59fc075 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -6025,6 +6025,22 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { getValue(I.getArgOperand(0)))); return nullptr; } + case Intrinsic::lround_i32: + case Intrinsic::lround_i64: + case Intrinsic::llround: { + unsigned Opcode; + MVT RetVT; + switch (Intrinsic) { + default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. + case Intrinsic::lround_i32: Opcode = ISD::LROUND; RetVT = MVT::i32; break; + case Intrinsic::lround_i64: Opcode = ISD::LROUND; RetVT = MVT::i64; break; + case Intrinsic::llround: Opcode = ISD::LLROUND; RetVT = MVT::i64; break; + } + + setValue(&I, DAG.getNode(Opcode, sdl, RetVT, + getValue(I.getArgOperand(0)))); + return nullptr; + } case Intrinsic::minnum: { auto VT = getValue(I.getArgOperand(0)).getValueType(); unsigned Opc = |