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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-27 17:46:40 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-27 17:46:40 +0000 |
commit | 6f2a526101bfef214aef8cae8dba4a9cce55b6fa (patch) | |
tree | 7fdf854c43b57af4354e0d48aec858b4e72b18be /llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | |
parent | b3cd5a1037d71e33b2519fcaf66e2978679f3c22 (diff) | |
download | llvm-6f2a526101bfef214aef8cae8dba4a9cce55b6fa.zip llvm-6f2a526101bfef214aef8cae8dba4a9cce55b6fa.tar.gz llvm-6f2a526101bfef214aef8cae8dba4a9cce55b6fa.tar.bz2 |
Add alignment value to allowsUnalignedMemoryAccess
Rename to allowsMisalignedMemoryAccess.
On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment,
and don't need to be split into multiple accesses. Vector loads with
an alignment of the element type are not uncommon in OpenCL code.
llvm-svn: 214055
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 4ccdb1d..e3d74da 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5725,9 +5725,10 @@ bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { unsigned SrcAS = RHS->getType()->getPointerAddressSpace(); // TODO: Handle 5 byte compare as 4-byte + 1 byte. // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. + // TODO: Check alignment of src and dest ptrs. if (!TLI->isTypeLegal(LoadVT) || - !TLI->allowsUnalignedMemoryAccesses(LoadVT, SrcAS) || - !TLI->allowsUnalignedMemoryAccesses(LoadVT, DstAS)) + !TLI->allowsMisalignedMemoryAccesses(LoadVT, SrcAS) || + !TLI->allowsMisalignedMemoryAccesses(LoadVT, DstAS)) ActuallyDoIt = false; } |