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| author | Alexandros Lamprineas <alexandros.lamprineas@arm.com> | 2021-07-31 08:46:20 +0100 |
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| committer | Alexandros Lamprineas <alexandros.lamprineas@arm.com> | 2021-07-31 09:51:28 +0100 |
| commit | 3094e5389b3dfb046eebcb549f7f4b814258863e (patch) | |
| tree | 9f4ffa1ec63e359956fbb8cd0d8ca4428fda8095 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | |
| parent | 29b263a34f1afbae9c95bf48eab7e8aac8132a80 (diff) | |
| download | llvm-3094e5389b3dfb046eebcb549f7f4b814258863e.zip llvm-3094e5389b3dfb046eebcb549f7f4b814258863e.tar.gz llvm-3094e5389b3dfb046eebcb549f7f4b814258863e.tar.bz2 | |
[AArch64] Add a Machine Value Type for 8 consecutive registers
Adds MVT::i64x8, a Machine Value Type needed for lowering inline assembly
operands which materialize a sequence of eight general purpose registers.
Differential Revision: https://reviews.llvm.org/D94096
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp')
0 files changed, 0 insertions, 0 deletions