aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
diff options
context:
space:
mode:
authorAlexander Richardson <alexrichardson@google.com>2025-05-19 17:26:05 -0700
committerGitHub <noreply@github.com>2025-05-19 17:26:05 -0700
commit07e2ba445df7d277e5195c0ec85b133735ea76e3 (patch)
treec2af349a81fd28ca304f96925338b78e5a508e0e /llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
parent90daed32a82ad2695d27db285ac36f579f2b270e (diff)
downloadllvm-07e2ba445df7d277e5195c0ec85b133735ea76e3.zip
llvm-07e2ba445df7d277e5195c0ec85b133735ea76e3.tar.gz
llvm-07e2ba445df7d277e5195c0ec85b133735ea76e3.tar.bz2
[AMDGPU] Set AS8 address width to 48 bits
Of the 128-bits of buffer descriptor only 48 bits are address bits, so following the discussion on https://discourse.llvm.org/t/clarifiying-the-semantics-of-ptrtoint/83987/54, the logic conclusion is to set the index width to 48 bits instead of the current value of 128. Most of the test changes are mechanical datalayout updates, but there is one actual change: the ptrmask test now uses .i48 instead of .i128 and I had to update SelectionDAGBuilder to correctly extend the mask. Reviewed By: krzysz00 Pull Request: https://github.com/llvm/llvm-project/pull/139419
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp15
1 files changed, 12 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 3ebd3a4..e32fcfe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7966,17 +7966,26 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
// On arm64_32, pointers are 32 bits when stored in memory, but
// zero-extended to 64 bits when in registers. Thus the mask is 32 bits to
- // match the index type, but the pointer is 64 bits, so the the mask must be
+ // match the index type, but the pointer is 64 bits, so the mask must be
// zero-extended up to 64 bits to match the pointer.
EVT PtrVT =
TLI.getValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
EVT MemVT =
TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
assert(PtrVT == Ptr.getValueType());
- assert(MemVT == Mask.getValueType());
- if (MemVT != PtrVT)
+ if (Mask.getValueType().getFixedSizeInBits() < MemVT.getFixedSizeInBits()) {
+ // For AMDGPU buffer descriptors the mask is 48 bits, but the pointer is
+ // 128-bit, so we have to pad the mask with ones for unused bits.
+ auto HighOnes = DAG.getNode(
+ ISD::SHL, sdl, PtrVT, DAG.getAllOnesConstant(sdl, PtrVT),
+ DAG.getShiftAmountConstant(Mask.getValueType().getFixedSizeInBits(),
+ PtrVT, sdl));
+ Mask = DAG.getNode(ISD::OR, sdl, PtrVT,
+ DAG.getZExtOrTrunc(Mask, sdl, PtrVT), HighOnes);
+ } else if (Mask.getValueType() != PtrVT)
Mask = DAG.getPtrExtOrTrunc(Mask, sdl, PtrVT);
+ assert(Mask.getValueType() == PtrVT);
setValue(&I, DAG.getNode(ISD::AND, sdl, PtrVT, Ptr, Mask));
return;
}