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| author | Craig Topper <craig.topper@intel.com> | 2019-02-05 06:13:06 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-02-05 06:13:06 +0000 |
| commit | f86eb00f122f3524e256b9a2059a3b37a25583ff (patch) | |
| tree | 9a5400ed6b9de1566b3bac4ed73bb48922638293 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp | |
| parent | 73f499771f84ffed1c2a7fb19593d05f3cd91ffd (diff) | |
| download | llvm-f86eb00f122f3524e256b9a2059a3b37a25583ff.zip llvm-f86eb00f122f3524e256b9a2059a3b37a25583ff.tar.gz llvm-f86eb00f122f3524e256b9a2059a3b37a25583ff.tar.bz2 | |
[X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them.
Summary:
We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly.
This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that.
Reviewers: rnk
Reviewed By: rnk
Subscribers: eraman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57641
llvm-svn: 353141
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions