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author | Eric Christopher <echristo@gmail.com> | 2014-07-23 22:34:13 +0000 |
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committer | Eric Christopher <echristo@gmail.com> | 2014-07-23 22:34:13 +0000 |
commit | f19d12ba3cb3a095224b0fc86a65134acf957139 (patch) | |
tree | cc3ed72dcfccd2debfe9ed16f549578f07924623 /llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | |
parent | 9f2a54c579807bd567a5fb43c9c472eb6527ec02 (diff) | |
download | llvm-f19d12ba3cb3a095224b0fc86a65134acf957139.zip llvm-f19d12ba3cb3a095224b0fc86a65134acf957139.tar.gz llvm-f19d12ba3cb3a095224b0fc86a65134acf957139.tar.bz2 |
Fix indenting.
llvm-svn: 213811
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp index 8380a6f..6029d8e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp @@ -51,19 +51,20 @@ ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) ResourcesModel = TII->CreateTargetScheduleState(&TM, nullptr); // This hard requirement could be relaxed, but for now // do not let it procede. - assert (ResourcesModel && "Unimplemented CreateTargetScheduleState."); - - unsigned NumRC = TRI->getNumRegClasses(); - RegLimit.resize(NumRC); - RegPressure.resize(NumRC); - std::fill(RegLimit.begin(), RegLimit.end(), 0); - std::fill(RegPressure.begin(), RegPressure.end(), 0); - for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), - E = TRI->regclass_end(); I != E; ++I) - RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF); - - ParallelLiveRanges = 0; - HorizontalVerticalBalance = 0; + assert(ResourcesModel && "Unimplemented CreateTargetScheduleState."); + + unsigned NumRC = TRI->getNumRegClasses(); + RegLimit.resize(NumRC); + RegPressure.resize(NumRC); + std::fill(RegLimit.begin(), RegLimit.end(), 0); + std::fill(RegPressure.begin(), RegPressure.end(), 0); + for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), + E = TRI->regclass_end(); + I != E; ++I) + RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF); + + ParallelLiveRanges = 0; + HorizontalVerticalBalance = 0; } unsigned |