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| author | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2024-10-29 10:52:20 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-29 10:52:20 +0000 |
| commit | c3260c65e86ac363aa3a39f084db66a8a1d1af7d (patch) | |
| tree | 172e22dba28c65e0a4c4857546fe1bf7c2fdae35 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | 7395ef5419a6438f0c48685bf00b7f151178743d (diff) | |
| download | llvm-c3260c65e86ac363aa3a39f084db66a8a1d1af7d.zip llvm-c3260c65e86ac363aa3a39f084db66a8a1d1af7d.tar.gz llvm-c3260c65e86ac363aa3a39f084db66a8a1d1af7d.tar.bz2 | |
[IR] Add `llvm.sincos` intrinsic (#109825)
This adds the `llvm.sincos` intrinsic, legalization, and lowering.
The `llvm.sincos` intrinsic takes a floating-point value and returns
both the sine and cosine (as a struct).
```
declare { float, float } @llvm.sincos.f32(float %Val)
declare { double, double } @llvm.sincos.f64(double %Val)
declare { x86_fp80, x86_fp80 } @llvm.sincos.f80(x86_fp80 %Val)
declare { fp128, fp128 } @llvm.sincos.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 } @llvm.sincos.ppcf128(ppc_fp128 %Val)
declare { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float> %Val)
```
The lowering is built on top of the existing FSINCOS ISD node, with
additional type legalization to allow for f16, f128, and vector values.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index a8042fc..c80da28 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -452,6 +452,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::UMULO: case ISD::FCANONICALIZE: case ISD::FFREXP: + case ISD::FSINCOS: case ISD::SADDSAT: case ISD::UADDSAT: case ISD::SSUBSAT: |