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author | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2025-02-11 09:01:30 +0000 |
---|---|---|
committer | GitHub <noreply@github.com> | 2025-02-11 09:01:30 +0000 |
commit | 701223ac20a45d23b9b01c8a514294eb16219d79 (patch) | |
tree | d65c2dfa42b392e0df846192bd47c27f4910085d /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
parent | 6a961dc03d802fb1f34b2b0cd8d09f427382dbdb (diff) | |
download | llvm-701223ac20a45d23b9b01c8a514294eb16219d79.zip llvm-701223ac20a45d23b9b01c8a514294eb16219d79.tar.gz llvm-701223ac20a45d23b9b01c8a514294eb16219d79.tar.bz2 |
[IR] Add llvm.sincospi intrinsic (#125873)
This adds the `llvm.sincospi` intrinsic, legalization, and lowering
(mostly reusing the lowering for sincos and frexp).
The `llvm.sincospi` intrinsic takes a floating-point value and returns
both the sine and cosine of the value multiplied by pi. It computes the
result more accurately than the naive approach of doing the
multiplication ahead of time, especially for large input values.
```
declare { float, float } @llvm.sincospi.f32(float %Val)
declare { double, double } @llvm.sincospi.f64(double %Val)
declare { x86_fp80, x86_fp80 } @llvm.sincospi.f80(x86_fp80 %Val)
declare { fp128, fp128 } @llvm.sincospi.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %Val)
declare { <4 x float>, <4 x float> } @llvm.sincospi.v4f32(<4 x float> %Val)
```
Currently, the default lowering of this intrinsic relies on the
`sincospi[f|l]` functions being available in the target's runtime (e.g.
libc).
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 416da1b..111b08a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -456,6 +456,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::FFREXP: case ISD::FMODF: case ISD::FSINCOS: + case ISD::FSINCOSPI: case ISD::SADDSAT: case ISD::UADDSAT: case ISD::SSUBSAT: @@ -1217,9 +1218,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) { return; break; - case ISD::FSINCOS: { - RTLIB::Libcall LC = - RTLIB::getFSINCOS(Node->getValueType(0).getVectorElementType()); + case ISD::FSINCOS: + case ISD::FSINCOSPI: { + EVT VT = Node->getValueType(0).getVectorElementType(); + RTLIB::Libcall LC = Node->getOpcode() == ISD::FSINCOS + ? RTLIB::getFSINCOS(VT) + : RTLIB::getSINCOSPI(VT); if (DAG.expandMultipleResultFPLibCall(LC, Node, Results)) return; break; |