diff options
| author | Nikita Popov <npopov@redhat.com> | 2024-06-28 08:36:49 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-28 08:36:49 +0200 |
| commit | 9df71d7673b5c98e1032d01be83724a45b42fafc (patch) | |
| tree | cf5f0c837110b4a753e71b0532d8e5ee6d487411 /llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | |
| parent | 519e0bb094bd9444b64ac62f2e8192543fdb94b9 (diff) | |
| download | llvm-9df71d7673b5c98e1032d01be83724a45b42fafc.zip llvm-9df71d7673b5c98e1032d01be83724a45b42fafc.tar.gz llvm-9df71d7673b5c98e1032d01be83724a45b42fafc.tar.bz2 | |
[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)
Similar to https://github.com/llvm/llvm-project/pull/96902, this adds
`getDataLayout()` helpers to Function and GlobalValue, replacing the
current `getParent()->getDataLayout()` pattern.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index de22d23..8f5b05b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -186,7 +186,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, Register SP = TLI->getStackPointerRegisterToSaveRestore(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); std::vector<TargetLowering::AsmOperandInfo> Ops = - TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, + TLI->ParseConstraints(Fn->getDataLayout(), TRI, *Call); for (TargetLowering::AsmOperandInfo &Op : Ops) { if (Op.Type == InlineAsm::isClobber) { @@ -570,7 +570,7 @@ FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) { SmallVector<EVT, 4> ValueVTs; for (auto &P : ValueMap) { ValueVTs.clear(); - ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(), + ComputeValueVTs(*TLI, Fn->getDataLayout(), P.first->getType(), ValueVTs); unsigned Reg = P.second; for (EVT VT : ValueVTs) { |