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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-11-02 13:17:30 -0700 |
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committer | Matt Arsenault <arsenm2@gmail.com> | 2022-11-02 16:05:34 -0700 |
commit | 4fed59ed41007c2380d6742f6a91178e2f35fa01 (patch) | |
tree | ac4594f89f064abd1501ce9ffa544bfd2023cb8a /llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | |
parent | 0efff7cdcb26917b9acd1a280911317ea12dc937 (diff) | |
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FunctionLoweringInfo: Use TLI member instead of finding it
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index b1e369d..bf67ef9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -369,8 +369,7 @@ void FunctionLoweringInfo::clear() { /// CreateReg - Allocate a single virtual register for the given type. Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { - return RegInfo->createVirtualRegister( - MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent)); + return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); } /// CreateRegs - Allocate the appropriate number of virtual registers of @@ -381,8 +380,6 @@ Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { /// will assign registers for each member or element. /// Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { - const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); - SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); |