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author | pvanhout <pierre.vanhoutryve@amd.com> | 2023-03-13 11:33:15 +0100 |
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committer | pvanhout <pierre.vanhoutryve@amd.com> | 2023-03-14 14:38:45 +0100 |
commit | 1f1fea6c380ef397f2a2416f14f8945d294a4682 (patch) | |
tree | 6442dc6975030dec8f0cecadc046232f9864e19c /llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | |
parent | 874c49f55454cb285282e6d184f809945c0beca1 (diff) | |
download | llvm-1f1fea6c380ef397f2a2416f14f8945d294a4682.zip llvm-1f1fea6c380ef397f2a2416f14f8945d294a4682.tar.gz llvm-1f1fea6c380ef397f2a2416f14f8945d294a4682.tar.bz2 |
Reland: [DAG/AMDGPU] Use UniformityAnalysis in DAGISel
Switch DAGISel over to UniformityAnalysis, which was one of the last remaining users of the DivergenceAnalysis.
No explosions seen during internal testing so this looks like a smooth transition.
Reviewed By: sameerds
Differential Revision: https://reviews.llvm.org/D145918
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 4766486..76ebdb4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -13,7 +13,7 @@ #include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/ADT/APInt.h" -#include "llvm/Analysis/LegacyDivergenceAnalysis.h" +#include "llvm/Analysis/UniformityAnalysis.h" #include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -83,7 +83,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, TLI = MF->getSubtarget().getTargetLowering(); RegInfo = &MF->getRegInfo(); const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); - DA = DAG->getDivergenceAnalysis(); + UA = DAG->getUniformityInfo(); // Check whether the function can return without sret-demotion. SmallVector<ISD::OutputArg, 4> Outs; @@ -381,8 +381,8 @@ Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { } Register FunctionLoweringInfo::CreateRegs(const Value *V) { - return CreateRegs(V->getType(), DA && DA->isDivergent(V) && - !TLI->requiresUniformRegister(*MF, V)); + return CreateRegs(V->getType(), UA && UA->isDivergent(V) && + !TLI->requiresUniformRegister(*MF, V)); } /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the |