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authorCraig Topper <craig.topper@sifive.com>2022-03-22 23:07:29 -0700
committerCraig Topper <craig.topper@sifive.com>2022-03-22 23:24:53 -0700
commit1a9b55b63a6e18a4692eeb795697cb61ca1b002f (patch)
treeba2f32b0e78344e6f62bdeb1241c6675bc9ab83c /llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
parent98fd3b359866f474ab1c097c22fb5c3be356b996 (diff)
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[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo
Instead of using operator[], use DenseMap::find to prevent default constructing an entry if it isn't already in the map.
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp9
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index b494551..e39ad73 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -445,9 +445,14 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
unsigned BitWidth = IntVT.getSizeInBits();
- Register DestReg = ValueMap[PN];
- if (!Register::isVirtualRegister(DestReg))
+ auto It = ValueMap.find(PN);
+ if (It == ValueMap.end())
return;
+
+ Register DestReg = It->second;
+ if (DestReg == 0)
+ return
+ assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg");
LiveOutRegInfo.grow(DestReg);
LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];