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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2019-08-01 23:27:28 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2019-08-01 23:27:28 +0000 |
| commit | 2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c (patch) | |
| tree | 91dc8f6a4635d24a9c93d1e5080a67b8baae69f8 /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | 9debb024d44db54b9453459d3bd98d28c20a163f (diff) | |
| download | llvm-2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c.zip llvm-2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c.tar.gz llvm-2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c.tar.bz2 | |
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
llvm-svn: 367633
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 8cf9138..592c0e9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -174,7 +174,7 @@ static unsigned findSinkableLocalRegDef(MachineInstr &MI) { if (RegDef) return 0; RegDef = MO.getReg(); - } else if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { + } else if (Register::isVirtualRegister(MO.getReg())) { // This is another use of a vreg. Don't try to sink it. return 0; } @@ -2028,7 +2028,7 @@ unsigned FastISel::createResultReg(const TargetRegisterClass *RC) { unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, unsigned OpNum) { - if (TargetRegisterInfo::isVirtualRegister(Op)) { + if (Register::isVirtualRegister(Op)) { const TargetRegisterClass *RegClass = TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF); if (!MRI.constrainRegClass(Op, RegClass)) { @@ -2236,7 +2236,7 @@ unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode, unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) { unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); - assert(TargetRegisterInfo::isVirtualRegister(Op0) && + assert(Register::isVirtualRegister(Op0) && "Cannot yet extract from physregs"); const TargetRegisterClass *RC = MRI.getRegClass(Op0); MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); |