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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-05-20 14:18:54 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-05-20 14:18:54 +0000 |
| commit | 70b1eee793e751c3a0b1084347e6645bced90da2 (patch) | |
| tree | 97f0f52e7031d148d9669c075f9a45626b8d0b46 /llvm/lib/CodeGen/RegisterScavenging.cpp | |
| parent | 42bbe77009b0875524f9f14b176c757393bf5da3 (diff) | |
| download | llvm-70b1eee793e751c3a0b1084347e6645bced90da2.zip llvm-70b1eee793e751c3a0b1084347e6645bced90da2.tar.gz llvm-70b1eee793e751c3a0b1084347e6645bced90da2.tar.bz2 | |
Skip entries with invalid indexes in the search loop in register scavenger
llvm-svn: 270219
Diffstat (limited to 'llvm/lib/CodeGen/RegisterScavenging.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegisterScavenging.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index b7836b4..2cd5233 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -400,11 +400,14 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, unsigned NeedAlign = RC->getAlignment(); unsigned SI = Scavenged.size(), Diff = UINT_MAX; + int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd(); for (unsigned I = 0; I < Scavenged.size(); ++I) { if (Scavenged[I].Reg != 0) continue; // Verify that this slot is valid for this register. int FI = Scavenged[I].FrameIndex; + if (FI < FIB || FI >= FIE) + continue; unsigned S = MFI.getObjectSize(FI); unsigned A = MFI.getObjectAlignment(FI); if (NeedSize > S || NeedAlign > A) @@ -425,7 +428,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, if (SI == Scavenged.size()) { // We need to scavenge a register but have no spill slot, the target // must know how to do it (if not, we'll assert below). - Scavenged.push_back(ScavengedInfo()); + Scavenged.push_back(ScavengedInfo(FIE)); } // Avoid infinite regress |