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author | Kazu Hirata <kazu@google.com> | 2021-11-28 10:04:54 -0800 |
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committer | Kazu Hirata <kazu@google.com> | 2021-11-28 10:04:54 -0800 |
commit | c73fc74ce0f85510ebedd9fe8bcad51d53f2465c (patch) | |
tree | 0a8278e9ed298fb78e33ba2d49d3d974f8c64059 /llvm/lib/CodeGen/RegAllocFast.cpp | |
parent | 8874ada906f6a2ae0c4aa978581a0c9c26b89ffd (diff) | |
download | llvm-c73fc74ce0f85510ebedd9fe8bcad51d53f2465c.zip llvm-c73fc74ce0f85510ebedd9fe8bcad51d53f2465c.tar.gz llvm-c73fc74ce0f85510ebedd9fe8bcad51d53f2465c.tar.bz2 |
[llvm] Use range-based for loops (NFC)
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocFast.cpp')
-rw-r--r-- | llvm/lib/CodeGen/RegAllocFast.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 68920e2..6653145 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -1258,8 +1258,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { // Free registers occupied by defs. // Iterate operands in reverse order, so we see the implicit super register // defs first (we added them earlier in case of <def,read-undef>). - for (unsigned I = MI.getNumOperands(); I-- > 0;) { - MachineOperand &MO = MI.getOperand(I); + for (MachineOperand &MO : llvm::reverse(MI.operands())) { if (!MO.isReg() || !MO.isDef()) continue; @@ -1362,8 +1361,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { // Free early clobbers. if (HasEarlyClobber) { - for (unsigned I = MI.getNumOperands(); I-- > 0; ) { - MachineOperand &MO = MI.getOperand(I); + for (MachineOperand &MO : llvm::reverse(MI.operands())) { if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber()) continue; // subreg defs don't free the full register. We left the subreg number @@ -1440,8 +1438,7 @@ void RegAllocFast::handleBundle(MachineInstr &MI) { MachineBasicBlock::instr_iterator BundledMI = MI.getIterator(); ++BundledMI; while (BundledMI->isBundledWithPred()) { - for (unsigned I = 0; I < BundledMI->getNumOperands(); ++I) { - MachineOperand &MO = BundledMI->getOperand(I); + for (MachineOperand &MO : BundledMI->operands()) { if (!MO.isReg()) continue; |