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| author | Mircea Trofin <mtrofin@google.com> | 2020-09-23 21:58:45 -0700 |
|---|---|---|
| committer | Mircea Trofin <mtrofin@google.com> | 2020-10-05 16:13:18 -0700 |
| commit | b268e24d4349d586334dd6f47aa99b2196b1046e (patch) | |
| tree | 13f7634cc4603f4d58c84f1db7a47f81aa5a9374 /llvm/lib/CodeGen/RegAllocBasic.cpp | |
| parent | 2ea8fec2cd566be77c9412aacb8e546bd0c36612 (diff) | |
| download | llvm-b268e24d4349d586334dd6f47aa99b2196b1046e.zip llvm-b268e24d4349d586334dd6f47aa99b2196b1046e.tar.gz llvm-b268e24d4349d586334dd6f47aa99b2196b1046e.tar.bz2 | |
[NFC][regalloc] Separate iteration from AllocationOrder
This separates the two concerns - encapsulation of traversal order; and
iteration.
Differential Revision: https://reviews.llvm.org/D88256
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocBasic.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocBasic.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index 8bbbbeb..83b5a05 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -261,7 +261,8 @@ Register RABasic::selectOrSplit(LiveInterval &VirtReg, // Check for an available register in this class. auto Order = AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); - while (Register PhysReg = Order.next()) { + for (MCRegister PhysReg : Order) { + assert(PhysReg.isValid()); // Check for interference in PhysReg switch (Matrix->checkInterference(VirtReg, PhysReg)) { case LiveRegMatrix::IK_Free: |