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| author | Andrei Safronov <andrei.safronov@espressif.com> | 2025-02-03 03:13:24 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-03 03:13:24 +0300 |
| commit | f6578c3d809b22d08524c3ae017c843f478d67e6 (patch) | |
| tree | db20e3f08b8ee6d1ab6cad0258531898537a819e /llvm/lib/CodeGen/ReachingDefAnalysis.cpp | |
| parent | 115bb87ad0a85d8ab4d907399db130cb1f2c63f2 (diff) | |
| download | llvm-f6578c3d809b22d08524c3ae017c843f478d67e6.zip llvm-f6578c3d809b22d08524c3ae017c843f478d67e6.tar.gz llvm-f6578c3d809b22d08524c3ae017c843f478d67e6.tar.bz2 | |
[Xtensa] Implement Windowed Register Option. (#124656)
This patch implements Xtensa ISA option "Windowed Register Option". It implements subtarget feature, instructions descriptions and support of these instructions in asm parser and disassembler.
This is the second version of the Windowed Register Option implementation ( previous implementation #121118). In this variant "checkRegister" function is placed in XtensaMCTargetDesc.
Diffstat (limited to 'llvm/lib/CodeGen/ReachingDefAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions