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| author | Marina Yatsina <marina.yatsina@intel.com> | 2018-01-22 13:24:10 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2018-01-22 13:24:10 +0000 |
| commit | e4d63a499d32d631041d6c1bcbd9f6e2309e690c (patch) | |
| tree | 8721c43707ca125f26fb274f048fd20763e1790a /llvm/lib/CodeGen/ReachingDefAnalysis.cpp | |
| parent | 9b36fd25419cf72907b7c0b3c34431f460d6ef45 (diff) | |
| download | llvm-e4d63a499d32d631041d6c1bcbd9f6e2309e690c.zip llvm-e4d63a499d32d631041d6c1bcbd9f6e2309e690c.tar.gz llvm-e4d63a499d32d631041d6c1bcbd9f6e2309e690c.tar.bz2 | |
Fixing warnings caused by commit 323095
Change-Id: I4e1f81db2f5382a820f4016c23b243e4d5aebf51
llvm-svn: 323114
Diffstat (limited to 'llvm/lib/CodeGen/ReachingDefAnalysis.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp index d24803a..6b131b2 100644 --- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -23,7 +23,7 @@ void ReachingDefAnalysis::enterBasicBlock( const LoopTraversal::TraversedMBBInfo &TraversedMBB) { MachineBasicBlock *MBB = TraversedMBB.MBB; - int MBBNumber = MBB->getNumber(); + unsigned MBBNumber = MBB->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); MBBReachingDefs[MBBNumber].resize(NumRegUnits); @@ -53,7 +53,7 @@ void ReachingDefAnalysis::enterBasicBlock( // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock *pred : MBB->predecessors()) { - assert(pred->getNumber() < MBBOutRegsInfos.size() && + assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() && "Should have pre-allocated MBBInfos for all MBBs"); const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()]; // Incoming is null if this is a backedge from a BB @@ -77,7 +77,7 @@ void ReachingDefAnalysis::enterBasicBlock( void ReachingDefAnalysis::leaveBasicBlock( const LoopTraversal::TraversedMBBInfo &TraversedMBB) { assert(!LiveRegs.empty() && "Must enter basic block first."); - int MBBNumber = TraversedMBB.MBB->getNumber(); + unsigned MBBNumber = TraversedMBB.MBB->getNumber(); assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number."); // Save register clearances at end of MBB - used by enterBasicBlock(). @@ -95,7 +95,7 @@ void ReachingDefAnalysis::leaveBasicBlock( void ReachingDefAnalysis::processDefs(MachineInstr *MI) { assert(!MI->isDebugValue() && "Won't process debug values"); - int MBBNumber = MI->getParent()->getNumber(); + unsigned MBBNumber = MI->getParent()->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); const MCInstrDesc &MCID = MI->getDesc(); @@ -174,7 +174,7 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { assert(InstIds.count(MI) && "Unexpected machine instuction."); int InstId = InstIds[MI]; int DefRes = ReachingDedDefaultVal; - int MBBNumber = MI->getParent()->getNumber(); + unsigned MBBNumber = MI->getParent()->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); int LatestDef = ReachingDedDefaultVal; |