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authorChristudasan Devadasan <christudasan.devadasan@amd.com>2024-01-24 07:08:43 +0530
committerGitHub <noreply@github.com>2024-01-24 07:08:43 +0530
commit230c13d59d0843c3b738920b85c341cc78a61fa9 (patch)
tree2b21ba0fb19a086167639d4a212b4d56d0e48e2c /llvm/lib/CodeGen/RDFGraph.cpp
parent7e50f006f7f652b9a5ac5ddd64deba5f1c9388a8 (diff)
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[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)
CSR SGPR spilling currently uses the early available physical VGPRs. It currently imposes a high register pressure while trying to allocate large VGPR tuples within the default register budget. This patch changes the spilling strategy by picking the VGPRs in the reverse order, the highest available VGPR first and later after regalloc shift them back to the lowest available range. With that, the initial VGPRs would be available for allocation and possibility of finding large number of contiguous registers will be more.
Diffstat (limited to 'llvm/lib/CodeGen/RDFGraph.cpp')
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