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| author | Luke Lau <luke@igalia.com> | 2025-04-23 18:43:55 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-23 18:43:55 +0800 |
| commit | 717efc0a994dfc5b2ed65ddb13b47fb917c9a467 (patch) | |
| tree | bb59aa5e168df862d570120fc3c2cb11a2d24df0 /llvm/lib/CodeGen/PrologEpilogInserter.cpp | |
| parent | b0524f332958b6e593868533127fd0651bdcf553 (diff) | |
| download | llvm-717efc0a994dfc5b2ed65ddb13b47fb917c9a467.zip llvm-717efc0a994dfc5b2ed65ddb13b47fb917c9a467.tar.gz llvm-717efc0a994dfc5b2ed65ddb13b47fb917c9a467.tar.bz2 | |
[RISCV] Support disjoint RISCVISD::OR_VL in combineOp_VLToVWOp_VL (#136820)
This handles combining fixed-length disjoint ors to vwadd[u].wv, as was
done for scalable vectors in #86929.
vwadd[u].vv patterns need to be handled separately with a pattern in a
separate patch due to the extends being sunk, see #136716.
Diffstat (limited to 'llvm/lib/CodeGen/PrologEpilogInserter.cpp')
0 files changed, 0 insertions, 0 deletions