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| author | Alexey Samsonov <vonosmas@gmail.com> | 2014-08-20 20:57:26 +0000 |
|---|---|---|
| committer | Alexey Samsonov <vonosmas@gmail.com> | 2014-08-20 20:57:26 +0000 |
| commit | ea0aee622e802bae9bc3f74f5109ee42245bd7e5 (patch) | |
| tree | d0cbcb088affa94f06840fd2a0e0a0381ad94e98 /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 75172a95678e79449df1375b6478b97bf4f2d21a (diff) | |
| download | llvm-ea0aee622e802bae9bc3f74f5109ee42245bd7e5.zip llvm-ea0aee622e802bae9bc3f74f5109ee42245bd7e5.tar.gz llvm-ea0aee622e802bae9bc3f74f5109ee42245bd7e5.tar.bz2 | |
Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.
llvm-svn: 216124
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 5a87fd9..b95e7c3 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -137,10 +137,10 @@ namespace { public: SchedulePostRATDList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - AliasAnalysis *AA, const RegisterClassInfo&, - TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, - SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs); + MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, + const RegisterClassInfo &, + TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, + SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs); ~SchedulePostRATDList(); @@ -193,11 +193,11 @@ INITIALIZE_PASS(PostRAScheduler, "post-RA-sched", "Post RA top-down list latency scheduler", false, false) SchedulePostRATDList::SchedulePostRATDList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - AliasAnalysis *AA, const RegisterClassInfo &RCI, - TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, - SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) - : ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { + MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, + const RegisterClassInfo &RCI, + TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, + SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) + : ScheduleDAGInstrs(MF, &MLI, /*IsPostRA=*/true), AA(AA), EndIndex(0) { const TargetMachine &TM = MF.getTarget(); const InstrItineraryData *InstrItins = @@ -269,7 +269,6 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); - MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); AliasAnalysis *AA = &getAnalysis<AliasAnalysis>(); TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>(); @@ -303,7 +302,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { DEBUG(dbgs() << "PostRAScheduler\n"); - SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode, + SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, CriticalPathRCs); // Loop over all of the basic blocks |