diff options
| author | Alexey Samsonov <vonosmas@gmail.com> | 2014-08-20 19:36:05 +0000 |
|---|---|---|
| committer | Alexey Samsonov <vonosmas@gmail.com> | 2014-08-20 19:36:05 +0000 |
| commit | 8968e6d1b02543d12e312f1be6edd152b89de584 (patch) | |
| tree | e0a9f8a8404b21f5f96a52db2fd9c2ac71349303 /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
| parent | d750723d291dc6cd9295b7b0643b71d8cd9fbab2 (diff) | |
| download | llvm-8968e6d1b02543d12e312f1be6edd152b89de584.zip llvm-8968e6d1b02543d12e312f1be6edd152b89de584.tar.gz llvm-8968e6d1b02543d12e312f1be6edd152b89de584.tar.bz2 | |
Fix null reference creation in ScheduleDAGInstrs constructor call.
Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.
This bug is reported by UBSan.
llvm-svn: 216118
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index a1f3e5b..5a87fd9 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -197,7 +197,7 @@ SchedulePostRATDList::SchedulePostRATDList( AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) - : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { + : ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { const TargetMachine &TM = MF.getTarget(); const InstrItineraryData *InstrItins = |