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authorMatt Arsenault <Matthew.Arsenault@amd.com>2025-01-23 09:06:26 +0700
committerGitHub <noreply@github.com>2025-01-23 09:06:26 +0700
commit15c2d4baf17292b4966d335846b30c50063f0265 (patch)
treee231ddce2a77a4b5ff2c98341fcc934db4f081ee /llvm/lib/CodeGen/PeepholeOptimizer.cpp
parentba70368f1380f8d22494fc8c100d2ab894a3cf94 (diff)
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PeepholeOpt: Remove check for subreg index on a def operand (#123943)
This is looking at operand 0 of a REG_SEQUENCE, which can never have a subregister index.
Diffstat (limited to 'llvm/lib/CodeGen/PeepholeOptimizer.cpp')
-rw-r--r--llvm/lib/CodeGen/PeepholeOptimizer.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index aec4aaa..48c25d5 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -426,8 +426,8 @@ public:
const MachineOperand &MODef = CopyLike.getOperand(0);
Dst.Reg = MODef.getReg();
- // If we have to compose sub-registers, bail.
- return MODef.getSubReg() == 0;
+ assert(MODef.getSubReg() == 0 && "cannot have subregister def in SSA");
+ return true;
}
bool RewriteCurrentSource(Register NewReg, unsigned NewSubReg) override {