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| author | Craig Topper <craig.topper@sifive.com> | 2022-04-28 09:21:13 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-04-28 09:58:30 -0700 |
| commit | ec11fbb1d682e9c3e67eafc036c92fe9200b40f5 (patch) | |
| tree | 406f2f371ba34cd88487d315414e1659d243bd8a /llvm/lib/CodeGen/ModuloSchedule.cpp | |
| parent | 8b687974842d2c3442091681fb4d3008ef5810a7 (diff) | |
| download | llvm-ec11fbb1d682e9c3e67eafc036c92fe9200b40f5.zip llvm-ec11fbb1d682e9c3e67eafc036c92fe9200b40f5.tar.gz llvm-ec11fbb1d682e9c3e67eafc036c92fe9200b40f5.tar.bz2 | |
[RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled.
This improves opportunities to use bset/bclr/binv. Unfortunately,
there are no W versions of these instrcutions so this isn't always
a clear win. If we use SLLW we get free sign extend and shift masking,
but need to put a 1 in a register and can't remove an or/xor. If
we use bset/bclr/binv we remove the immediate materializationg and
logic op, but might need a mask on the shift amount and sext.w.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D124096
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
0 files changed, 0 insertions, 0 deletions