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| author | Chen Zheng <czhengsz@cn.ibm.com> | 2022-04-08 03:24:46 -0400 |
|---|---|---|
| committer | Chen Zheng <czhengsz@cn.ibm.com> | 2022-08-08 21:34:20 -0400 |
| commit | d9004dfbabc62887f09775297436792077ce4496 (patch) | |
| tree | 95d30a719d45eeb2c831de019d65e96b9bb9a389 /llvm/lib/CodeGen/ModuloSchedule.cpp | |
| parent | 2eb50cee11ccbfac71eeb7687b9f136d95fc7f52 (diff) | |
| download | llvm-d9004dfbabc62887f09775297436792077ce4496.zip llvm-d9004dfbabc62887f09775297436792077ce4496.tar.gz llvm-d9004dfbabc62887f09775297436792077ce4496.tar.bz2 | |
[PowerPC] mapping hardward loop intrinsics to powerpc pseudo
Map hardware loop intrinsics loop_decrement and set_loop_iteration
to the new PowerPC pseudo instructions, so that the hardware loop
intrinsics will be expanded to normal cmp+branch form or ctrloop
form based on the CTR register usage on MIR level.
Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D123366
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
0 files changed, 0 insertions, 0 deletions