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author | Hendrik Greving <hgreving@google.com> | 2020-05-27 17:12:58 -0700 |
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committer | Hendrik Greving <hgreving@google.com> | 2020-05-29 07:01:27 -0700 |
commit | d8f2814c913847b1d0e9167dce5973eea3600c7e (patch) | |
tree | 7c7496557eb5c9e443d33dc11974b35935df7f0a /llvm/lib/CodeGen/ModuloSchedule.cpp | |
parent | 9819976032c5af8d9109f2077e637c8303e4d6df (diff) | |
download | llvm-d8f2814c913847b1d0e9167dce5973eea3600c7e.zip llvm-d8f2814c913847b1d0e9167dce5973eea3600c7e.tar.gz llvm-d8f2814c913847b1d0e9167dce5973eea3600c7e.tar.bz2 |
[ModuloSchedule] Allow illegal phis to be moved across stages.
Fixes a trivial but impactful bug where we did not move illegal phis across stages. This
led to incorrect mappings in certain cases.
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
-rw-r--r-- | llvm/lib/CodeGen/ModuloSchedule.cpp | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp index aa35996..a4b994b 100644 --- a/llvm/lib/CodeGen/ModuloSchedule.cpp +++ b/llvm/lib/CodeGen/ModuloSchedule.cpp @@ -1629,18 +1629,21 @@ void PeelingModuloScheduleExpander::moveStageBetweenBlocks( MachineInstr *MI = &*I++; if (MI->isPHI()) { // This is an illegal PHI. If we move any instructions using an illegal - // PHI, we need to create a legal Phi - Register PhiR = MI->getOperand(0).getReg(); - auto RC = MRI.getRegClass(PhiR); - Register NR = MRI.createVirtualRegister(RC); - MachineInstr *NI = BuildMI(*DestBB, DestBB->getFirstNonPHI(), DebugLoc(), - TII->get(TargetOpcode::PHI), NR) - .addReg(PhiR) - .addMBB(SourceBB); - BlockMIs[{DestBB, CanonicalMIs[MI]}] = NI; - CanonicalMIs[NI] = CanonicalMIs[MI]; - Remaps[PhiR] = NR; - continue; + // PHI, we need to create a legal Phi. + if (getStage(MI) != Stage) { + // The legal Phi is not necessary if the illegal phi's stage + // is being moved. + Register PhiR = MI->getOperand(0).getReg(); + auto RC = MRI.getRegClass(PhiR); + Register NR = MRI.createVirtualRegister(RC); + MachineInstr *NI = BuildMI(*DestBB, DestBB->getFirstNonPHI(), + DebugLoc(), TII->get(TargetOpcode::PHI), NR) + .addReg(PhiR) + .addMBB(SourceBB); + BlockMIs[{DestBB, CanonicalMIs[MI]}] = NI; + CanonicalMIs[NI] = CanonicalMIs[MI]; + Remaps[PhiR] = NR; + } } if (getStage(MI) != Stage) continue; |