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| author | Michael Liao <michael.hliao@gmail.com> | 2020-09-09 16:48:03 -0400 |
|---|---|---|
| committer | Michael Liao <michael.hliao@gmail.com> | 2020-09-17 11:04:17 -0400 |
| commit | c3492a1aa1b98c8d81b0969d52cea7681f0624c2 (patch) | |
| tree | 7020da70f62be8bdf685204f82ae477cd9cb789b /llvm/lib/CodeGen/ModuloSchedule.cpp | |
| parent | 34b27b9441d27ef886ea22b3bb75b357a5ec707b (diff) | |
| download | llvm-c3492a1aa1b98c8d81b0969d52cea7681f0624c2.zip llvm-c3492a1aa1b98c8d81b0969d52cea7681f0624c2.tar.gz llvm-c3492a1aa1b98c8d81b0969d52cea7681f0624c2.tar.bz2 | |
[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.
- Need to lower COPY from SGPR to VGPR to a real instruction as the
standard COPY is used where the source and destination are from the
same register bank so that we potentially coalesc them together and
save one COPY. Considering that, backend optimizations, such as CSE,
won't handle them. However, the copy from SGPR to VGPR always needs
materializing to a native instruction, it should be lowered into a
real one before other backend optimizations.
Differential Revision: https://reviews.llvm.org/D87556
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
0 files changed, 0 insertions, 0 deletions